Job Summary
Company Name
Adept Talent Search & Recruitment Consultants
Locations
Bengaluru / Bangalore, Chennai
Experience
3 – 8 years
Keywords / Skills
Education
B.E/B.Tech, M.E/M.Tech/MS
Function
Manufacturing/ Engineering/ R&D
Role
• Design Manager/ Engineer
• R & D Manager
• R & D Manager
Industry
• Consultancy
• Semiconductor
• Semiconductor
Salary
6.00 – 25.00 lacs
Summary
Responsible for Physical Design and Verification• 3 to 8 years of experience in PD• Experience in the complete PD flow from RTL to GDSIIBangalore/Chennai
Posted On
9th Oct 2015
Job Description
Perform Synthesis, Floor planning & Placement.
Perform Clock tree synthesis, timing and SI driven routing.
Perform Post route timing optimization.
Perform EM analysis and closure.
Power planning of the device by following their custom requirements.
Placement iterations for timing between the blocks, CTS and Routing.
Static Noise Analysis and Fixing.
Performed Formal Verification using Conformal LEC at all phases in the design.
Physical Verification: ERC, DRC, LVS, ANTDRC analysis, debugging and fixes.
Key Skill(s)
Physical Design
Floor Planning
DFT
PD
GDS
About Company
Our client is a reputed MNC well known name in the Consulting and IT and semiconductor design
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Physical Design Engineer
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